1. Field of the Invention
The present invention relates to the field of semiconductor integrated circuit (IC) manufacturing, and more specifically, to a method of protecting a seed layer for electroplating.
2. Discussion of Related Art
In 1965, Gordon Moore first observed that the number of transistors per unit area on a chip appeared to double approximately every 18 months. Ever since then, the semiconductor industry has managed to introduce new designs and processes on schedule to deliver the improvement in device density projected by the so-called Moore's Law. In particular, major enhancements in optics and photolithography have reduced the critical dimension (CD) that can be successfully patterned in the features on a chip or other substrate. At the same time, significant improvements in doping, deposition, and etch have decreased the concentration, depth, and thickness that can be precisely achieved across the substrate.
The transistors in a chip are formed in a semiconductor material on a substrate, such as a wafer. The transistors are then wired with multiple layers of interconnects. The interconnects are formed from an electrically conducting material and are isolated by an electrically insulating material. The electrically conducting material may be formed with an electroplating process and planarized with a chemical-mechanical polishing (CMP) process.
FIG. 1(a) shows a substrate 90 that includes a device 95. The substrate 90 is covered with an insulator 100. The insulator 100 is patterned and etched to produce an opening 105. A barrier layer 110 is formed over the opening 105 and the insulator 100. Then a seed layer 120 is formed over the barrier layer 110. An insulating defect 125 and a conducting defect 126 may appear on the seed layer 120.
FIG. 1(b) shows the results of electroplating a conductor 130 onto the surface of a seed layer 120 that already has the insulating defect 125 and the conducting defect 126. The insulating defect 125 will cause a void 127 to form nearby within the bulk of the conductor 130. The conducting defect 126 will cause a bump 128 to form at the electroplated upper surface 131 of the conductor 130.
FIG. 1(c) shows the results of planarizing the conductor 130 with a CMP process. The portion of the barrier layer 110 that is outside the original opening 105 may be removed by a CMP process or an etch process. The planarized upper surface 132 of the conductor 130 becomes flat and level with the planarized upper surface 102 of the insulator 100. An interconnect 135 becomes inset or inlaid within the original opening 105. The interconnect 135 may include a line 135B overlying a plug 135A.
A bump 128 at the surface of the conductor 130 that is small will usually be removed by planarization, but a bump 128 that is very large may affect the flatness of the planarized upper surface 132 of the interconnect 135.
A void 127 that is small and deep may remain embedded within the conductor 130, but a void 127 that is large and shallow may be opened up to form a surface defect 129, such as a depression, as shown in FIG. 1(c). A surface defect 129 may adversely affect the next layer of interconnect, depending on whether the surface defect 129 is subsequently filled with an insulator or a conductor.
After planarization, the original insulating defect 125 and the original conducting defect 126 may remain embedded within the conductor 130 if the defects 125, 126 are located within the original opening 105.
The defects 125, 126, and 127 may affect the resistance or capacitance of the interconnect 135, depending on whether the defects are electrically insulating or electrically conducting. Consequently, performance of the device 95 may be degraded. Furthermore, manufacturing yield, as well as device reliability, may also suffer.
Thus, what is needed is a method of protecting a seed layer for electroplating.